1. Field of the Invention
The present invention generally relates to improving the quality of gate oxides in complex MOSFET devices, and, more particularly, to the formation of conductive channel regions below gate electrodes of complex MOSFET devices.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors. Typically, present-day integrated circuits are implemented by millions of MOS transistors which are formed on a semiconductor substrate with a given surface area.
Basically, MOS transistors act as electronic switching elements, wherein a current through a channel region formed between source and drain regions of a MOS transistor is controlled by a gate electrode which is typically disposed over the channel region, independent of whether a PMOS transistor or an NMOS transistor is considered. Particularly, the conductivity state of a transistor is changed by a voltage applied to the gate electrode passing a so-called threshold voltage (Vt). In general, the threshold voltage depends nontrivially on the transistor's properties, such as size, material, etc.
However, as semiconductor devices and device features have become smaller in order to comply with requirements set by advanced integration densities, conventional fabrication techniques have been pushed to their limits, challenging their abilities to produce finely defined features at presently required scales. Consequently, developers are faced at each scale with problems and constraints imposed by scaling limitations which arise with semiconductor devices continuing to decrease in size.
A severe issue met by developers when attempting to exceed current technology nodes is given by constraints on maximum thicknesses of gate dielectrics in advanced gate electrodes set by the requirement of implementing a sufficiently high capacitive coupling between the gate electrode and the underlying channel region so as to reliably control a conductivity state of the channel region, while suppressing leakage currents of the gate electrode into the channel region through the gate dielectric. With decreasing gate length, this becomes an increasingly critical issue because the capacitive coupling of the gate electrode to the channel region strongly depends on the thickness of the gate dielectric. Particularly, for maintaining a sufficiently high capacitive coupling, a gate dielectric with a sufficiently small thickness has to be provided. On the other hand, the probability of tunneling of charge-carriers through the gate dielectric and, therefore, the presence of a tunneling current between gate electrode and channel region increases with decreasing thickness of the gate dielectric. This situation has been addressed by using so-called high-k dielectrics having k-values greater than 5 which allow, on the one hand, increasing the thickness of the gate dielectric so as to reduce the tunneling currents, while, on the other hand, maintaining a sufficiently high capacitive coupling between the gate electrode and the channel region due to its high electrical permeability.
In present integrated circuits formed on semiconductor substrates, a large number of different semiconductor devices and device structures are formed in order to implement a plurality of required functions on a microchip. For example, current integrated circuits may comprise a huge number (on the order of millions) of EG devices and SG devices which are disposed at different device areas of the semiconductor substrate on which the integrated circuit is to be formed on. Due to current high integration densities of complex semiconductor devices at present reaching the deep submicron regime, it is not hard to see that fabrication methods are highly complex and involve a large number of different processes to form individual semiconductor devices and semiconductor device structures on a given surface of a semiconductor wafer in accordance with a desired layout. In current fabrication processes, processing time may be reduced by performing a multitude of different semiconductor devices in parallel when possible, which also helps to save manufacturing costs.
EG devices have a much thicker gate oxide when compared to SG devices because EG devices are usually used as input-output devices (I/O devices) at peripheral regions of integrated circuits where usually comparably high voltages are applied (possibly up to about 15 V). The risk of gate dielectric breakdown, i.e., a breakthrough of gate oxide, is reduced with increasing gate oxide thickness, due to gate electrodes with thicker gate oxides supporting higher gate voltages. Consequently, device failure is prevented.
In current fabrication processes, EG devices and SG devices are fabricated in parallel, wherein a thick gate oxide layer is formed over EG and SG device regions, followed by an etching process for etching of the thick gate oxide from above the SG device regions. Subsequently, gate oxides are formed over the SG device regions and a gate etch is performed to pattern gate electrodes in EG device regions and SG device regions. The thick gate oxides for EG devices are conventionally created by high temperature oxidation (HTO) processes which show faster oxide growth rates as compared to low temperature oxidation processes, such as oxide deposition by chemical vapor deposition (CVD) at about 600° C., for instance, used in TEOS processes. Conventional high temperature oxidation processes are performed as low pressure chemical vapor deposition (LPCVD) deposition processes at temperatures of about 900° C. using a combination of dichlorosilane SiH2CL2 and N2O.
When etching off the thick gate oxide layer or high thermal oxide (HTO) layer on top of SG devices, it is hard to avoid also removing semiconductor material formed below the SG devices, said semiconductor material often comprising a small silicon/germanium layer, a so-called channel silicon/germanium (cSiGe), when PMOS devices are considered. As a result, a surface roughness of silicon material surfaces is created in SG device regions. Due to the surface roughness of semiconductor material surfaces in the SG device regions, interfaces between the semiconductor material and layers to be formed on the semiconductor material in the SG device regions are deteriorated in quality. The inventors understood that surfaces of poor quality increase a density of charge traps in subsequently-formed interfaces of poor quality. Consequently, undesired variations due to interface charge trapping effects and poor charge carrier mobility characteristics arise which become intolerable for complex semiconductor device structures at present technology nodes, particularly at technology nodes smaller than 50 nm, or preferably smaller than 30 nm.
It is, therefore, desirable to provide a method which allows improving the fabrication of semiconductor device structures to provide gate oxides having superior quality. Particularly, it is desirable to provide improved charge carrier mobility at interfaces adjacent to channel regions and reducing variations caused by interface charge trapping, and particularly to avoid interface charge trapping due to providing interfaces of superior quality adjacent to channel regions of semiconductor device structures.